Optical subassemblies such as transmitters or receivers are commonly used in a variety of different applications such as 40/100G small form-factor pluggable (SFP) transceiver connector, quad small form-factor pluggable (QSPF) connectors, and QSPF28 connectors. These connectors often stack the electrical IC and photonic chip which reduces power consumption, package size, and cost and may improve performance. However, shrinking CMOS node sizes for electrical ICs require higher I/O and denser routing which increases impedance and inductance values for electrical routing. This problem only grows worse as the electrical IC performs additional functions such as driving external circuits or performing data recovery/error correction. Moreover, using multiple lanes of differential high speed I/O (e.g., 40/100G or +100G transceivers using advanced modulation schemes) may also require additional routing relative to a system that has less bandwidth or functionality.
Typically, the PCB is communicatively coupled to the electrical IC via one or more redistribution layers in the photonic chip. For example, the transmitter may include a plurality of wire bonds that connect the PCB to bond pads on the photonic chip. From there, the photonic chip uses its redistribution layers to carry electrical signals to the electrical IC. However, as the number of I/O routes increases, the redistribution layers in the photonic chips may be insufficient for routing electrical signals between the PCB and the electrical IC.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation.